1. Field of the Invention
This invention relates to a synchronization code detecting apparatus for cell search in a code division multiple access (CDMA) system and, more particularly, to a synchronization code detecting apparatus for cell search in a wideband code division multiple access (W-CDMA) system of 3rd Generation Partnership Project (3GPP). The synchronization code detecting apparatus adopts a fully compensated structure or a partially compensated structure so that it can mitigate the adverse effect on cell search caused by the frequency offset.
2. Description of the Related Art
The CDMA cellular systems using a technique of direct sequence spread spectrum code division multiple accesses greatly increase their channel capacity. These systems have attracted much attention in the recent research of mobile communication systems. Generally speaking, the bandwidth efficiency of a CDMA system is better than other multiple access systems such as Frequency Division Multiple Access (FDMA) and Time Division Multiple Access (TDMA). Moreover, cell planning of a CDMA system is relatively simple. Therefore, CDMA systems will be prevalent in future mobile communication systems. It should be noted that 3GPP W-CDMA Frequency Division Duplex (FDD) systems have been adopted for use as one of the standards for International Mobile Telecommunications-2000 (IMT-2000), the third generation systems.
In a CDMA cellular system, a method using user equipment (UE) for searching the best cell is referred to as “cell search”. High-speed cell search is crucial for reducing the switched-on delay (initial search) of the user equipment, increasing the standby time (idle mode search), and keeping a good quality of communication link in handover (active mode search).
Referring to FIG. 1 for understanding the frame structure of a 3GPP W-CDMA/FDD system. Firstly, in a 3GPP W-CDMA/FDD system, cell search is usually accomplished in three stages which includes two specially designed synchronization channels (SCH) and a common pilot channel (CPICH). In the first stage 110, the primary synchronization channel (PSCH) 111 is used for time slot synchronization. The PSCH 111 includes a primary synchronization code (PSC) defined as acp, wherein “a”(=±1) depending on whether diversity transmission of the base station exists. In the second stage 120, the secondary synchronization channel (SSCH) 121 is used for frame/code group identification. The SSCH 121 includes secondary synchronization code (SSCs) defined as acs, wherein the coefficient a is equivalent to that of the PSCH 111. In the third stage 130, the common pilot channel 131 is used for determining a downlink scrambling code. As illustrated in the figure, there are 15 time slots in 10 ms radio frame. In addition, the system uses the speed of 3.84 Mchips/sec and therefore each radio frame consists of 38400 chips. That is to say, each time slot consists of 2560 chips. Moreover, both the PSC and the SSC of 256-chip long are transmitted at the beginning of each time slot. Thus, the PSC and SSC are time aligned for every 2560 chips long.
In recent years, high-speed cell search methods for use in CDMA cellular systems have been disclosed, for example, in U.S. Pat. No. 6,185,244, issued to Nystrom, et al., entitled “Cell searching in a CDMA communications system”. In this prior art invention, a special coding structure is disclosed for more effectively acquiring a long code and frame timing during a cell search in a CDMA communications system. A code set of length M Q-ary code words including symbols from a set of Q short codes is defined with certain properties. The primary property to be satisfied is that no cyclic shift of a code word yields a valid code word. The other properties to be satisfied are that there is a one-to-one mapping between a long code message and a valid code word, and a decoder should be able to find both the random shift (thereby finding the frame timing) and the transmitted code word (i.e., its associated long code indication message) in the presence of interference and noise, with some degree of accuracy and reasonable complexity.
There are yet other cell search methods as follows:
U.S. Pat. No. 6,289,007, issued to Kim, et al., entitled “Method for Acquiring A Cell Site Station in Asynchronous CDMA Cellular Communication Systems”; and U.S. Pat. No. 6,038,250, issued to Shou, et al., entitled “Initial Synchronization Method And Receiver for Direct Sequence (DS)-CDMA Inter Base Station Asynchronous Cellular System.”
However, the prior art cell search technology usually for use in a wideband code division multiple access (W-CDMA) system of 3rd Generation Partnership Project (3GPP) involves two basic assumptions. The first assumption is that the sampling from the output of the chip-matched filter is an ideal sampling. Nevertheless, the actual sampling from the output of the chip-matched filter is a non-ideal sampling. The second assumption is that the chip rate of the transmitter is precisely known to the receiver (i.e. there is no clock offset). In other words, no frequency offset is set for the carrier frequency of the incoming signals. Actually, the frequency offset is caused by the instability in frequency of the transistor oscillator of the subscriber apparatus. For mobile user equipment, the frequency of the incoming signal carrier may have a frequency offset and therefore results in an uncertain range of the carrier frequency. The frequency offset results in two effects in the base frequency band: (1) phase rotation, and (2) clock offset. The clock offset has not been considered in the prior art. In the past, a phase rotation caused by a frequency offset can be eliminated by a synchronization code matched filter of a non-coherent structure. This technique is disclosed in “Initial frequency acquisition in W-CDMA,” Y. P. E. Wang and T. Ottosson, IEEE Proc. VTC'99, Vol. 2, pp. 1013–1017, Sept. 1999.
However, the clock offset caused by the frequency offset exists between a base station and a user equipment, and this has not been considered in the prior art. Referring now to Table 1 that shows the relation between clock drift and time at different frequency offsets. For example, at a 12 kHz frequency offset, the sampling points in a 30 ms code frame involve 0.69 times of chip time offset that is equivalent to a 6 ppm frequency offset. This will result in an information error and a time increase in cell search. FIGS. 2(a) and 2(b) do not show the prior art technology. They show the output of the primary code matched filter under the clock drift effect caused by frequency offset. These figures show the results of the signal level decrease and the interference increase when the optimum sampling point shifts with time. According to the present inventions, clock offset stems from the frequency inaccuracies of the oscillators are not efficiently treated. However, performance of the cell search becomes intolerable in high frequency offset scenarios (e.g. frequency offset larger than 8 kHz). Therefore, there is a need to provide a novel cell search apparatus to effectively eliminate the frequency offset effect.